Notice of Violation of IEEE Publication PrinciplesA 2-5GHz low jitter 0.13 őľm CMOS PLL using a dynamic current matching charge-pump and a noise attenuating loop-filter [frequency synthesizer application].
Notice of Violation of IEEE Publication PrinciplesA 2-5GHz low jitter 0.13 őľm CMOS PLL using a dynamic current matching charge-pump and a noise attenuating loop-filter [frequency synthesizer application].
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Notice of Violation of IEEE Publication PrinciplesA 2-5GHz low jitter 0.13 őľm CMOS PLL using a dynamic current matching charge-pump and a noise attenuating loop-filter [frequency synthesizer application].
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