A sub-threshold FPGA with low-swing dual-VDD interconnect in 90nm CMOS. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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rdfs:label	A sub-threshold FPGA with low-swing dual-VDD interconnect in 90nm CMOS. (xsd:string)
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dc:title	A sub-threshold FPGA with low-swing dual-VDD interconnect in 90nm CMOS. (xsd:string)
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