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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/cicc/TyhachWSHNWCPKR04>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bonnie_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chiakang_Sung>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gopinath_Rangan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Henry_Kim>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jeffrey_Tyhach>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Johnson_Tan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Joseph_Huang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Khai_Nguyen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Philip_Pan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tzung-Chin_Chang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xiaobao_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yan_Chong>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FCICC.2004.1358843>
foaf:homepage <https://doi.org/10.1109/CICC.2004.1358843>
dc:identifier DBLP conf/cicc/TyhachWSHNWCPKR04 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FCICC.2004.1358843 (xsd:string)
dcterms:issued 2004 (xsd:gYear)
rdfs:label A 90 nm FPGA I/O buffer design with 1.6 Gbps data rate for source-synchronous system and 300 MHz clock rate for external memory interface. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bonnie_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chiakang_Sung>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gopinath_Rangan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Henry_Kim>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jeffrey_Tyhach>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Johnson_Tan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Joseph_Huang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Khai_Nguyen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Philip_Pan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tzung-Chin_Chang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xiaobao_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yan_Chong>
swrc:pages 431-434 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/cicc/2004>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/cicc/TyhachWSHNWCPKR04/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/cicc/TyhachWSHNWCPKR04>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/cicc/cicc2004.html#TyhachWSHNWCPKR04>
rdfs:seeAlso <https://doi.org/10.1109/CICC.2004.1358843>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/cicc>
dc:title A 90 nm FPGA I/O buffer design with 1.6 Gbps data rate for source-synchronous system and 300 MHz clock rate for external memory interface. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document