Power-smart system-on-chip architecture for embedded cryptosystems.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/codes/MuresanVZG05
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2005
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Power-smart system-on-chip architecture for embedded cryptosystems.
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DES, current flattening in hardware, power analysis attack resistant architecture, power-smart system-on-chip, voltage scaling
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Power-smart system-on-chip architecture for embedded cryptosystems.
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