Intra- and inter-processor hybrid performance modeling for MPSoC architectures.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/codes/OpheldersCC08
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/codes/OpheldersCC08
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Frank_E._B._Ophelders
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Henk_Corporaal
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Samarjit_Chakraborty
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1145%2F1450135.1450156
>
foaf:
homepage
<
https://doi.org/10.1145/1450135.1450156
>
dc:
identifier
DBLP conf/codes/OpheldersCC08
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1145%2F1450135.1450156
(xsd:string)
dcterms:
issued
2008
(xsd:gYear)
rdfs:
label
Intra- and inter-processor hybrid performance modeling for MPSoC architectures.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Frank_E._B._Ophelders
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Henk_Corporaal
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Samarjit_Chakraborty
>
swrc:
pages
91-96
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/codes/2008
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/codes/OpheldersCC08/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/codes/OpheldersCC08
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/codes/codes2008.html#OpheldersCC08
>
rdfs:
seeAlso
<
https://doi.org/10.1145/1450135.1450156
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/codes
>
dc:
subject
performance analysis, simulation, system-on-chip
(xsd:string)
dc:
title
Intra- and inter-processor hybrid performance modeling for MPSoC architectures.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document