Methodology for multi-granularity embedded processor power model generation for an ESL design flow.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/codes/ParkPKD08
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2008
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Methodology for multi-granularity embedded processor power model generation for an ESL design flow.
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embedded processor, esl, power modeling, system-on-chip
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Methodology for multi-granularity embedded processor power model generation for an ESL design flow.
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