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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/codes/RoseCKSH96>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fred_Rose>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/John_Shackleton>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sanjaya_Kumar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Todd_Carpenter>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Todd_Steeves_Honeywell>
foaf:homepage <http://dx.doi.org/doi.ieeecomputersociety.org%2F10.1109%2FHCS.1996.492231>
foaf:homepage <https://doi.ieeecomputersociety.org/10.1109/HCS.1996.492231>
dc:identifier DBLP conf/codes/RoseCKSH96 (xsd:string)
dc:identifier DOI doi.ieeecomputersociety.org%2F10.1109%2FHCS.1996.492231 (xsd:string)
dcterms:issued 1996 (xsd:gYear)
rdfs:label A Model for the Coanalysis of Hardware and Software Architectures. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Fred_Rose>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/John_Shackleton>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sanjaya_Kumar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Todd_Carpenter>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Todd_Steeves_Honeywell>
swrc:pages 94-103 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/codes/1996>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/codes/RoseCKSH96/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/codes/RoseCKSH96>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/codes/codes1996.html#RoseCKSH96>
rdfs:seeAlso <https://doi.ieeecomputersociety.org/10.1109/HCS.1996.492231>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/codes>
dc:subject VHDL, performance modeling, hardware/software codesign, RASSP (xsd:string)
dc:title A Model for the Coanalysis of Hardware and Software Architectures. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document