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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/codes/SheePC05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Newton_Cheung>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Seng_Lin_Shee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sri_Parameswaran>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1084834.1084908>
foaf:homepage <https://doi.org/10.1145/1084834.1084908>
dc:identifier DBLP conf/codes/SheePC05 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1084834.1084908 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
rdfs:label Novel architecture for loop acceleration: a case study. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Newton_Cheung>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Seng_Lin_Shee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sri_Parameswaran>
swrc:pages 297-302 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/codes/2005>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/codes/SheePC05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/codes/SheePC05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/codes/codes2005.html#SheePC05>
rdfs:seeAlso <https://doi.org/10.1145/1084834.1084908>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/codes>
dc:subject ASIP, architecture, coprocessor, hardware/software partitioning, latency hiding, loop acceleration, loop optimization, loop pipelining, tightly coupled (xsd:string)
dc:title Novel architecture for loop acceleration: a case study. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document