Novel architecture for loop acceleration: a case study.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/codes/SheePC05
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2005
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Novel architecture for loop acceleration: a case study.
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ASIP, architecture, coprocessor, hardware/software partitioning, latency hiding, loop acceleration, loop optimization, loop pipelining, tightly coupled
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Novel architecture for loop acceleration: a case study.
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