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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/coolchips/HagiwaraHKAENTN18>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Akira_Tsukamoto>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Anh_Tran>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Binh_Nguyen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Cong-Kha_Pham>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Duong_Nguyen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fumio_Arakawa>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hayato_Nomura>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hoan_Hyunh>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ikuo_Kudoh>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kesami_Hagiwara>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Oleg_Endo>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shumpei_Kawasaki>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tomoichi_Hayashi>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FCoolChips.2018.8373084>
foaf:homepage <https://doi.org/10.1109/CoolChips.2018.8373084>
dc:identifier DBLP conf/coolchips/HagiwaraHKAENTN18 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FCoolChips.2018.8373084 (xsd:string)
dcterms:issued 2018 (xsd:gYear)
rdfs:label A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC for IoT, edge AI and robotic applications. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Akira_Tsukamoto>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Anh_Tran>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Binh_Nguyen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Cong-Kha_Pham>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Duong_Nguyen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Fumio_Arakawa>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hayato_Nomura>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hoan_Hyunh>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ikuo_Kudoh>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kesami_Hagiwara>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Oleg_Endo>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shumpei_Kawasaki>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tomoichi_Hayashi>
swrc:pages 1-3 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/coolchips/2018>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/coolchips/HagiwaraHKAENTN18/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/coolchips/HagiwaraHKAENTN18>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/coolchips/coolchips2018.html#HagiwaraHKAENTN18>
rdfs:seeAlso <https://doi.org/10.1109/CoolChips.2018.8373084>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/coolchips>
dc:title A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC for IoT, edge AI and robotic applications. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document