An 80 Gbps dependable multicore communication SoC with PCI express I/F and intelligent interrupt controller.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/coolchips/OtaniKNIUAAMHBS11
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/coolchips/OtaniKNIUAAMHBS11
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Atsuyuki_Ikeya
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Hiroyuki_Kondo
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Itaru_Nonomura
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Katsushi_Asahina
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Kazutami_Arimoto
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Minoru_Uemura
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Mitsuhisa_Sato
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Shin%27ichi_Miura
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Sugako_Otani
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Taisuke_Boku
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Toshihiro_Hanawa
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FCOOLCHIPS.2011.5890920
>
foaf:
homepage
<
https://doi.org/10.1109/COOLCHIPS.2011.5890920
>
dc:
identifier
DBLP conf/coolchips/OtaniKNIUAAMHBS11
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FCOOLCHIPS.2011.5890920
(xsd:string)
dcterms:
issued
2011
(xsd:gYear)
rdfs:
label
An 80 Gbps dependable multicore communication SoC with PCI express I/F and intelligent interrupt controller.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Atsuyuki_Ikeya
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Hiroyuki_Kondo
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Itaru_Nonomura
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Katsushi_Asahina
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Kazutami_Arimoto
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Minoru_Uemura
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Mitsuhisa_Sato
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Shin%27ichi_Miura
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Sugako_Otani
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Taisuke_Boku
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Toshihiro_Hanawa
>
swrc:
pages
1-3
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/coolchips/2011
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/coolchips/OtaniKNIUAAMHBS11/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/coolchips/OtaniKNIUAAMHBS11
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/coolchips/coolchips2011.html#OtaniKNIUAAMHBS11
>
rdfs:
seeAlso
<
https://doi.org/10.1109/COOLCHIPS.2011.5890920
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/coolchips
>
dc:
title
An 80 Gbps dependable multicore communication SoC with PCI express I/F and intelligent interrupt controller.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document