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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/coolchips/WalterSOSBCNSEH20>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alexander_Oefelein>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andr%E2%88%9A%C2%A9_Scharfe>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dennis_Walter>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Farkas_Csaszar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Florian_Schraut>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Heiner_Bauer>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Holger_Eisenreich>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/J%E2%88%9A%E2%88%82rg_Schreiter>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Robert_Niebsch>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sebastian_H%E2%88%9A%E2%88%82ppner>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FCOOLCHIPS49199.2020.9097639>
foaf:homepage <https://doi.org/10.1109/COOLCHIPS49199.2020.9097639>
dc:identifier DBLP conf/coolchips/WalterSOSBCNSEH20 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FCOOLCHIPS49199.2020.9097639 (xsd:string)
dcterms:issued 2020 (xsd:gYear)
rdfs:label A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alexander_Oefelein>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andr%E2%88%9A%C2%A9_Scharfe>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dennis_Walter>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Farkas_Csaszar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Florian_Schraut>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Heiner_Bauer>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Holger_Eisenreich>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/J%E2%88%9A%E2%88%82rg_Schreiter>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Robert_Niebsch>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sebastian_H%E2%88%9A%E2%88%82ppner>
swrc:pages 1-3 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/coolchips/2020>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/coolchips/WalterSOSBCNSEH20/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/coolchips/WalterSOSBCNSEH20>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/coolchips/coolchips2020.html#WalterSOSBCNSEH20>
rdfs:seeAlso <https://doi.org/10.1109/COOLCHIPS49199.2020.9097639>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/coolchips>
dc:title A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document