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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/cse/WangWCSH09>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/I-Wei_Wu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jean_Jyh-Jiun_Shann>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jyh-Shian_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wei-Chung_Hsu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yu-Sheng_Chen>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FCSE.2009.100>
foaf:homepage <https://doi.org/10.1109/CSE.2009.100>
dc:identifier DBLP conf/cse/WangWCSH09 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FCSE.2009.100 (xsd:string)
dcterms:issued 2009 (xsd:gYear)
rdfs:label Reducing Code Size by Graph Coloring Register Allocation and Assignment Algorithm for Mixed-Width ISA Processor. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/I-Wei_Wu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jean_Jyh-Jiun_Shann>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jyh-Shian_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wei-Chung_Hsu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yu-Sheng_Chen>
swrc:pages 174-181 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/cse/2009>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/cse/WangWCSH09/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/cse/WangWCSH09>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/cse/cse2009-2.html#WangWCSH09>
rdfs:seeAlso <https://doi.org/10.1109/CSE.2009.100>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/cse>
dc:title Reducing Code Size by Graph Coloring Register Allocation and Assignment Algorithm for Mixed-Width ISA Processor. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document