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dc:creator <https://dblp.l3s.de/d2r/resource/authors/Danijela_Efnusheva>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-319-57264-2%5F7>
foaf:homepage <https://doi.org/10.1007/978-3-319-57264-2_7>
dc:identifier DBLP conf/csoc/EfnushevaT17 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-319-57264-2%5F7 (xsd:string)
dcterms:issued 2017 (xsd:gYear)
rdfs:label Design of Processor in Memory with RISC-modified Memory-Centric Architecture. (xsd:string)
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foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Danijela_Efnusheva>
swrc:pages 70-81 (xsd:string)
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dc:title Design of Processor in Memory with RISC-modified Memory-Centric Architecture. (xsd:string)
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rdf:type swrc:InProceedings
rdf:type foaf:Document