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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/csps/WangSJ17>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Lingyu_Shen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Min_Jia>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xuedong_Wang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-981-10-6571-2%5F211>
foaf:homepage <https://doi.org/10.1007/978-981-10-6571-2_211>
dc:identifier DBLP conf/csps/WangSJ17 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-981-10-6571-2%5F211 (xsd:string)
dcterms:issued 2017 (xsd:gYear)
rdfs:label The Design and Optimization of DDR3 Controller Based on FPGA. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Lingyu_Shen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Min_Jia>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xuedong_Wang>
swrc:pages 1744-1750 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/csps/2017>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/csps/WangSJ17/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/csps/WangSJ17>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/csps/csps2017.html#WangSJ17>
rdfs:seeAlso <https://doi.org/10.1007/978-981-10-6571-2_211>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/csps>
dc:title The Design and Optimization of DDR3 Controller Based on FPGA. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document