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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/csse/LiuCLHLCLT22>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dehong_Liu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gang_Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jinlong_Liu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jun_Li>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Junjian_Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ke_Tang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Liang_Hu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F3569966.3571191>
foaf:homepage <https://doi.org/10.1145/3569966.3571191>
dc:identifier DBLP conf/csse/LiuCLHLCLT22 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F3569966.3571191 (xsd:string)
dcterms:issued 2022 (xsd:gYear)
rdfs:label Research on High Performance Domestic Chip Architecture Based on Digital Grid Edge Computing. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dehong_Liu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gang_Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jinlong_Liu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jun_Li>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Junjian_Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ke_Tang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Liang_Hu>
swrc:pages 695-701 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/csse/2022>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/csse/LiuCLHLCLT22/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/csse/LiuCLHLCLT22>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/csse/csse2022.html#LiuCLHLCLT22>
rdfs:seeAlso <https://doi.org/10.1145/3569966.3571191>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/csse>
dc:title Research on High Performance Domestic Chip Architecture Based on Digital Grid Edge Computing. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document