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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/dac/AdirABPS05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Allon_Adir>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Eyal_Bin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hezi_Azatchi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kirill_Shoikhet>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ofer_Peled>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1065579.1065785>
foaf:homepage <https://doi.org/10.1145/1065579.1065785>
dc:identifier DBLP conf/dac/AdirABPS05 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1065579.1065785 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
rdfs:label A generic micro-architectural test plan approach for microprocessor verification. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Allon_Adir>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Eyal_Bin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hezi_Azatchi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kirill_Shoikhet>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ofer_Peled>
swrc:pages 769-774 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/dac/2005>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/dac/AdirABPS05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/dac/AdirABPS05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/dac/dac2005.html#AdirABPS05>
rdfs:seeAlso <https://doi.org/10.1145/1065579.1065785>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/dac>
dc:subject coverage, dynamic verification, generic test plan, micro-architecture, test generation (xsd:string)
dc:title A generic micro-architectural test plan approach for microprocessor verification. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document