Fast and accurate parasitic capacitance models for layout-aware.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/dac/AgarwalSYV04
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2004
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Fast and accurate parasitic capacitance models for layout-aware.
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analog synthesis, layout aware, parasitic estimation
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Fast and accurate parasitic capacitance models for layout-aware.
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