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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/dac/AgarwalSYV04>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Anuradha_Agarwal>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hemanth_Sampath>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ranga_Vemuri>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Veena_Yelamanchili>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F996566.996610>
foaf:homepage <https://doi.org/10.1145/996566.996610>
dc:identifier DBLP conf/dac/AgarwalSYV04 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F996566.996610 (xsd:string)
dcterms:issued 2004 (xsd:gYear)
rdfs:label Fast and accurate parasitic capacitance models for layout-aware. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Anuradha_Agarwal>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hemanth_Sampath>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ranga_Vemuri>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Veena_Yelamanchili>
swrc:pages 145-150 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/dac/2004>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/dac/AgarwalSYV04/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/dac/AgarwalSYV04>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/dac/dac2004.html#AgarwalSYV04>
rdfs:seeAlso <https://doi.org/10.1145/996566.996610>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/dac>
dc:subject analog synthesis, layout aware, parasitic estimation (xsd:string)
dc:title Fast and accurate parasitic capacitance models for layout-aware. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document