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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/dac/BadarogluTDWMVG02>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Georges_G._E._Gielen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hugo_De_Man>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ingrid_Verbauwhede>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kris_Tiri>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mustafa_Badaroglu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Piet_Wambacq>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/St%E2%88%9A%C2%A9phane_Donnay>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F513918.514021>
foaf:homepage <https://doi.org/10.1145/513918.514021>
dc:identifier DBLP conf/dac/BadarogluTDWMVG02 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F513918.514021 (xsd:string)
dcterms:issued 2002 (xsd:gYear)
rdfs:label Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Georges_G._E._Gielen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hugo_De_Man>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ingrid_Verbauwhede>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kris_Tiri>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mustafa_Badaroglu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Piet_Wambacq>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/St%E2%88%9A%C2%A9phane_Donnay>
swrc:pages 399-404 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/dac/2002>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/dac/BadarogluTDWMVG02/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/dac/BadarogluTDWMVG02>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/dac/dac2002.html#BadarogluTDWMVG02>
rdfs:seeAlso <https://doi.org/10.1145/513918.514021>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/dac>
dc:subject clock distribution networks, di/dt noise, low-noise digital design, optimization, substrate noise, supply current shaping (xsd:string)
dc:title Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document