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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/dac/BaoVSMRPCYSFKM19>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alessio_Spessot>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Anabela_Veloso>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Anda_Mocuta>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Arnaud_Furn%E2%88%9A%C2%A9mont>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Davide_Crotti>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Farrukh_Yasin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gouri_Sankar_Kar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Julien_Ryckaert>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Manu_Perumkunnil>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Philippe_Matagne>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sushil_Sakhare>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Trong_Huynh_Bao>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F3316781.3317886>
foaf:homepage <https://doi.org/10.1145/3316781.3317886>
dc:identifier DBLP conf/dac/BaoVSMRPCYSFKM19 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F3316781.3317886 (xsd:string)
dcterms:issued 2019 (xsd:gYear)
rdfs:label Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alessio_Spessot>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Anabela_Veloso>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Anda_Mocuta>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Arnaud_Furn%E2%88%9A%C2%A9mont>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Davide_Crotti>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Farrukh_Yasin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gouri_Sankar_Kar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Julien_Ryckaert>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Manu_Perumkunnil>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Philippe_Matagne>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sushil_Sakhare>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Trong_Huynh_Bao>
swrc:pages 13 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/dac/2019>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/dac/BaoVSMRPCYSFKM19/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/dac/BaoVSMRPCYSFKM19>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/dac/dac2019.html#BaoVSMRPCYSFKM19>
rdfs:seeAlso <https://doi.org/10.1145/3316781.3317886>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/dac>
dc:title Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document