High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/dac/BorosRP00
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High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system.
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High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system.
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