Area-efficient instruction set synthesis for reconfigurable system-on-chip designs.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/dac/BriskKS04
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2004
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Area-efficient instruction set synthesis for reconfigurable system-on-chip designs.
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compiler, field-programmable gate array (FPGA), integer linear programming (ILP), resource sharing
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Area-efficient instruction set synthesis for reconfigurable system-on-chip designs.
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