A combined feasibility and performance macromodel for analog circuits.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/dac/DingV05
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/dac/DingV05
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Mengmeng_Ding
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Ranga_Vemuri
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1145%2F1065579.1065600
>
foaf:
homepage
<
https://doi.org/10.1145/1065579.1065600
>
dc:
identifier
DBLP conf/dac/DingV05
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1145%2F1065579.1065600
(xsd:string)
dcterms:
issued
2005
(xsd:gYear)
rdfs:
label
A combined feasibility and performance macromodel for analog circuits.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Mengmeng_Ding
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Ranga_Vemuri
>
swrc:
pages
63-68
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/dac/2005
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/dac/DingV05/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/dac/DingV05
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/dac/dac2005.html#DingV05
>
rdfs:
seeAlso
<
https://doi.org/10.1145/1065579.1065600
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/dac
>
dc:
subject
active learning, feasibility models, performance macromodeling
(xsd:string)
dc:
title
A combined feasibility and performance macromodel for analog circuits.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document