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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/dac/DuYG89>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/David_Hung-Chang_Du>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/S._H._Yen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Subbarao_Ghanta>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F74382.74475>
foaf:homepage <https://doi.org/10.1145/74382.74475>
dc:identifier DBLP conf/dac/DuYG89 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F74382.74475 (xsd:string)
dcterms:issued 1989 (xsd:gYear)
rdfs:label On the General False Path Problem in Timing Analysis. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/David_Hung-Chang_Du>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/S._H._Yen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Subbarao_Ghanta>
swrc:pages 555-560 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/dac/1989>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/dac/DuYG89/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/dac/DuYG89>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/dac/dac89.html#DuYG89>
rdfs:seeAlso <https://doi.org/10.1145/74382.74475>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/dac>
dc:subject Timing Verification, Logic Simulation, VLSI circuit, Timing Analysis, False path, Graph Theory. (xsd:string)
dc:title On the General False Path Problem in Timing Analysis. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document