Architecture-adaptive range limit windowing for simulated annealing FPGA placement.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/dac/EguroHS05
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2005
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Architecture-adaptive range limit windowing for simulated annealing FPGA placement.
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architecture-adaptive, placement, range limiting, reconfigurable logic, simulated annealing, windowing
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Architecture-adaptive range limit windowing for simulated annealing FPGA placement.
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