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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/dac/EisnerSHNNV00>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Cindy_Eisner>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Irit_Shitsevalov>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ken_Valk>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kyle_L._Nelson>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Russ_Hoover>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wayne_G._Nation>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F337292.337757>
foaf:homepage <https://doi.org/10.1145/337292.337757>
dc:identifier DBLP conf/dac/EisnerSHNNV00 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F337292.337757 (xsd:string)
dcterms:issued 2000 (xsd:gYear)
rdfs:label A methodology for formal design of hardware control with application to cache coherence protocols. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Cindy_Eisner>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Irit_Shitsevalov>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ken_Valk>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kyle_L._Nelson>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Russ_Hoover>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wayne_G._Nation>
swrc:pages 724-729 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/dac/2000>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/dac/EisnerSHNNV00/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/dac/EisnerSHNNV00>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/dac/dac2000.html#EisnerSHNNV00>
rdfs:seeAlso <https://doi.org/10.1145/337292.337757>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/dac>
dc:title A methodology for formal design of hardware control with application to cache coherence protocols. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document