An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/dac/HanBBCJ04
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2004
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An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory.
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data transfer architecture, memory server, message passing, multiprocessor SoC, network interface, network on chip
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An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory.
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