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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/dac/HortaLTP02>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/David_B._Parlour>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/David_E._Taylor>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Edson_L._Horta>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/John_W._Lockwood>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F513918.514007>
foaf:homepage <https://doi.org/10.1145/513918.514007>
dc:identifier DBLP conf/dac/HortaLTP02 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F513918.514007 (xsd:string)
dcterms:issued 2002 (xsd:gYear)
rdfs:label Dynamic hardware plugins in an FPGA with partial run-time reconfiguration. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/David_B._Parlour>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/David_E._Taylor>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Edson_L._Horta>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/John_W._Lockwood>
swrc:pages 343-348 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/dac/2002>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/dac/HortaLTP02/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/dac/HortaLTP02>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/dac/dac2002.html#HortaLTP02>
rdfs:seeAlso <https://doi.org/10.1145/513918.514007>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/dac>
dc:subject FPG, IP, Internet, hardware, modularity, network, packet, partial RTR, platform computing, reconfiguration, routing (xsd:string)
dc:title Dynamic hardware plugins in an FPGA with partial run-time reconfiguration. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document