Automatic synthesis of clock gating logic with controlled netlist perturbation.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/dac/Hurst08
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2008
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Automatic synthesis of clock gating logic with controlled netlist perturbation.
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clock gating, dynamic power, logic optimization, low power
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Automatic synthesis of clock gating logic with controlled netlist perturbation.
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