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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/dac/LiuKWC18>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chang_Wu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dae_Hee_Kim>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Deming_Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xinheng_Liu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F3225209.3225214>
foaf:homepage <https://doi.org/10.1145/3225209.3225214>
dc:identifier DBLP conf/dac/LiuKWC18 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F3225209.3225214 (xsd:string)
dcterms:issued 2018 (xsd:gYear)
rdfs:label Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chang_Wu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dae_Hee_Kim>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Deming_Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xinheng_Liu>
swrc:pages 1:1-1:8 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/dac/2018slip>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/dac/LiuKWC18/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/dac/LiuKWC18>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/dac/slip2018.html#LiuKWC18>
rdfs:seeAlso <https://doi.org/10.1145/3225209.3225214>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/dac>
dc:title Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document