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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/dac/LiuNPS00>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andrzej_J._Strojwas>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Lawrence_T._Pileggi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sani_R._Nassif>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ying_Liu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F337292.337365>
foaf:homepage <https://doi.org/10.1145/337292.337365>
dc:identifier DBLP conf/dac/LiuNPS00 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F337292.337365 (xsd:string)
dcterms:issued 2000 (xsd:gYear)
rdfs:label Impact of interconnect variations on the clock skew of a gigahertz microprocessor. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andrzej_J._Strojwas>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Lawrence_T._Pileggi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sani_R._Nassif>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ying_Liu>
swrc:pages 168-171 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/dac/2000>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/dac/LiuNPS00/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/dac/LiuNPS00>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/dac/dac2000.html#LiuNPS00>
rdfs:seeAlso <https://doi.org/10.1145/337292.337365>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/dac>
dc:title Impact of interconnect variations on the clock skew of a gigahertz microprocessor. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document