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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/dac/LuoYYB05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jia_Yu_0008>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jun_Yang_0002>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Laxmi_N._Bhuyan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yan_Luo>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1065579.1065766>
foaf:homepage <https://doi.org/10.1145/1065579.1065766>
dc:identifier DBLP conf/dac/LuoYYB05 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1065579.1065766 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
rdfs:label Low power network processor design using clock gating. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jia_Yu_0008>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jun_Yang_0002>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Laxmi_N._Bhuyan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yan_Luo>
swrc:pages 712-715 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/dac/2005>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/dac/LuoYYB05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/dac/LuoYYB05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/dac/dac2005.html#LuoYYB05>
rdfs:seeAlso <https://doi.org/10.1145/1065579.1065766>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/dac>
dc:subject low power, network processors (xsd:string)
dc:title Low power network processor design using clock gating. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document