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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/dac/LyseckyVT04>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Frank_Vahid>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Roman_L._Lysecky>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sheldon_X.-D._Tan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F996566.996819>
foaf:homepage <https://doi.org/10.1145/996566.996819>
dc:identifier DBLP conf/dac/LyseckyVT04 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F996566.996819 (xsd:string)
dcterms:issued 2004 (xsd:gYear)
rdfs:label Dynamic FPGA routing for just-in-time FPGA compilation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Frank_Vahid>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Roman_L._Lysecky>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sheldon_X.-D._Tan>
swrc:pages 954-959 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/dac/2004>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/dac/LyseckyVT04/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/dac/LyseckyVT04>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/dac/dac2004.html#LyseckyVT04>
rdfs:seeAlso <https://doi.org/10.1145/996566.996819>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/dac>
dc:subject FPGA, codesign, configurable logic, dynamic optimization, hardware/software partitioning, just-in-time compilation, place and route, platforms, system-on-a-chip, warp processors (xsd:string)
dc:title Dynamic FPGA routing for just-in-time FPGA compilation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document