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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/dac/ManeatisKMMS03>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Iain_McClatchie>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jaeha_Kim>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jay_Maxey>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/John_G._Maneatis>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Manjusha_Shankaradas>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F775832.776006>
foaf:homepage <https://doi.org/10.1145/775832.776006>
dc:identifier DBLP conf/dac/ManeatisKMMS03 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F775832.776006 (xsd:string)
dcterms:issued 2003 (xsd:gYear)
rdfs:label Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Iain_McClatchie>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jaeha_Kim>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jay_Maxey>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/John_G._Maneatis>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Manjusha_Shankaradas>
swrc:pages 688-690 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/dac/2003>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/dac/ManeatisKMMS03/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/dac/ManeatisKMMS03>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/dac/dac2003.html#ManeatisKMMS03>
rdfs:seeAlso <https://doi.org/10.1145/775832.776006>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/dac>
dc:subject PLL, adaptive bandwidth, analog circuits, clock generation, clock multiplication, frequency synthesis, phase-locked loop, self biased (xsd:string)
dc:title Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document