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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/dac/MassoudMBW98>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jacob_K._White_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Steve_S._Majors>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tareq_Bustami>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yehia_Massoud>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F277044.277194>
foaf:homepage <https://doi.org/10.1145/277044.277194>
dc:identifier DBLP conf/dac/MassoudMBW98 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F277044.277194 (xsd:string)
dcterms:issued 1998 (xsd:gYear)
rdfs:label Layout Techniques for Minimizing On-Chip Interconnect Self Inductance. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jacob_K._White_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Steve_S._Majors>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tareq_Bustami>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yehia_Massoud>
swrc:pages 566-571 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/dac/1998>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/dac/MassoudMBW98/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/dac/MassoudMBW98>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/dac/dac98.html#MassoudMBW98>
rdfs:seeAlso <https://doi.org/10.1145/277044.277194>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/dac>
dc:title Layout Techniques for Minimizing On-Chip Interconnect Self Inductance. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document