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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/dac/MetzgenN05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dominic_Nancekievill>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Paul_Metzgen>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1065579.1065692>
foaf:homepage <https://doi.org/10.1145/1065579.1065692>
dc:identifier DBLP conf/dac/MetzgenN05 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1065579.1065692 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
rdfs:label Multiplexer restructuring for FPGA implementation cost reduction. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dominic_Nancekievill>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Paul_Metzgen>
swrc:pages 421-426 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/dac/2005>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/dac/MetzgenN05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/dac/MetzgenN05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/dac/dac2005.html#MetzgenN05>
rdfs:seeAlso <https://doi.org/10.1145/1065579.1065692>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/dac>
dc:subject FPGA, busses, logic optimization, multiplexers, recoding, restructuring, synthesis (xsd:string)
dc:title Multiplexer restructuring for FPGA implementation cost reduction. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document