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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/dac/PangR08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Katarzyna_Radecka>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yu_Pang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1391469.1391574>
foaf:homepage <https://doi.org/10.1145/1391469.1391574>
dc:identifier DBLP conf/dac/PangR08 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1391469.1391574 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
rdfs:label Optimizing imprecise fixed-point arithmetic circuits specified by Taylor Series through arithmetic transform. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Katarzyna_Radecka>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yu_Pang>
swrc:pages 397-402 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/dac/2008>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/dac/PangR08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/dac/PangR08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/dac/dac2008.html#PangR08>
rdfs:seeAlso <https://doi.org/10.1145/1391469.1391574>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/dac>
dc:subject DSP circuit synthesis, Taylor Series, error analysis, optimization (xsd:string)
dc:title Optimizing imprecise fixed-point arithmetic circuits specified by Taylor Series through arithmetic transform. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document