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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/dac/RajaramHM04>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Anand_Rajaram>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jiang_Hu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rabi_N._Mahapatra>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F996566.996574>
foaf:homepage <https://doi.org/10.1145/996566.996574>
dc:identifier DBLP conf/dac/RajaramHM04 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F996566.996574 (xsd:string)
dcterms:issued 2004 (xsd:gYear)
rdfs:label Reducing clock skew variability via cross links. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Anand_Rajaram>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jiang_Hu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rabi_N._Mahapatra>
swrc:pages 18-23 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/dac/2004>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/dac/RajaramHM04/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/dac/RajaramHM04>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/dac/dac2004.html#RajaramHM04>
rdfs:seeAlso <https://doi.org/10.1145/996566.996574>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/dac>
dc:subject VLSI, clock network synthesis, physical design, variation (xsd:string)
dc:title Reducing clock skew variability via cross links. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document