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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/dac/RajaramP08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Anand_Rajaram>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/David_Z._Pan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1391469.1391654>
foaf:homepage <https://doi.org/10.1145/1391469.1391654>
dc:identifier DBLP conf/dac/RajaramP08 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1391469.1391654 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
rdfs:label Robust chip-level clock tree synthesis for SOC designs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Anand_Rajaram>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/David_Z._Pan>
swrc:pages 720-723 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/dac/2008>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/dac/RajaramP08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/dac/RajaramP08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/dac/dac2008.html#RajaramP08>
rdfs:seeAlso <https://doi.org/10.1145/1391469.1391654>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/dac>
dc:subject chip-level CTS, clock network, physical design (xsd:string)
dc:title Robust chip-level clock tree synthesis for SOC designs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document