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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/dac/RichardsonHHZSL02>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Julian_Lewis>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Lun_Bin_Huang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Naresh_Soni>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nick_Richardson>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Razak_Hossain>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tommy_Zounes>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F513918.514080>
foaf:homepage <https://doi.org/10.1145/513918.514080>
dc:identifier DBLP conf/dac/RichardsonHHZSL02 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F513918.514080 (xsd:string)
dcterms:issued 2002 (xsd:gYear)
rdfs:label The iCOREtm 520 MHz synthesizable CPU core. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Julian_Lewis>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Lun_Bin_Huang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Naresh_Soni>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nick_Richardson>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Razak_Hossain>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tommy_Zounes>
swrc:pages 640-645 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/dac/2002>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/dac/RichardsonHHZSL02/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/dac/RichardsonHHZSL02>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/dac/dac2002.html#RichardsonHHZSL02>
rdfs:seeAlso <https://doi.org/10.1145/513918.514080>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/dac>
dc:subject ASIC, CPU, branch-prediction, cache, embedded, high-frequency, microarchitecture, pipeline, st20, synthesis (xsd:string)
dc:title The iCOREtm 520 MHz synthesizable CPU core. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document