A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/dac/StojanovicBDW06
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2006
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A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors.
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error correcting codes, instruction queue, reliability
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A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors.
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