Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/dac/SuhKL05
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2005
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Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs.
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MPSoC, cache coherence, heterogeneous, inter-processor communication, real-time and embedded systems
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Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs.
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