RDE-based transistor-level gate simulation for statistical static timing analysis.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/dac/TangZBM10
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2010
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RDE-based transistor-level gate simulation for statistical static timing analysis.
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non-Monte Carlo, statistical static timing analysis, transistor-level modeling
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RDE-based transistor-level gate simulation for statistical static timing analysis.
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