Leveraging sequential equivalence checking to enable system-level to RTL flows.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/dac/UrardMGC08
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2008
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Leveraging sequential equivalence checking to enable system-level to RTL flows.
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RTL models, equivalence checking, formal verification, high-level synthesis, system-level models
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Leveraging sequential equivalence checking to enable system-level to RTL flows.
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