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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/dac/VladimirescuWKBKDNJL87>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alon_Kifir>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andrei_Vladimirescu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/David_Weiss>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/K._C._Ng>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Karja_Danuwidjaja>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Manolis_Katevenis>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Niraj_Jain>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Steven_Lass>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zvika_Bronstein>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F37888.37901>
foaf:homepage <https://doi.org/10.1145/37888.37901>
dc:identifier DBLP conf/dac/VladimirescuWKBKDNJL87 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F37888.37901 (xsd:string)
dcterms:issued 1987 (xsd:gYear)
rdfs:label A Vector Hardware Accelerator with Circuit Simulation Emphasis. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alon_Kifir>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andrei_Vladimirescu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/David_Weiss>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/K._C._Ng>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Karja_Danuwidjaja>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Manolis_Katevenis>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Niraj_Jain>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Steven_Lass>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zvika_Bronstein>
swrc:pages 89-94 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/dac/1987>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/dac/VladimirescuWKBKDNJL87/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/dac/VladimirescuWKBKDNJL87>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/dac/dac87.html#VladimirescuWKBKDNJL87>
rdfs:seeAlso <https://doi.org/10.1145/37888.37901>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/dac>
dc:title A Vector Hardware Accelerator with Circuit Simulation Emphasis. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document