Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/dac/WangCSC09
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2009
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Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications.
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Steiner graph, gated bus, power efficiency
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Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications.
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