Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/dac/YuP10
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Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms.
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L2 cache partitioning, off-chip bandwidth reduction
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Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms.
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