On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/dac/ZhaoPRFMCSY07
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On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise.
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On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise.
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