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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/dac/ZouLSWCYC20>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jianli_Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jun_Yu_0010>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Peng_Zou>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xiao_Shi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yao-Wen_Chang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yingjie_Wu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhifeng_Lin>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FDAC18072.2020.9218569>
foaf:homepage <https://doi.org/10.1109/DAC18072.2020.9218569>
dc:identifier DBLP conf/dac/ZouLSWCYC20 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FDAC18072.2020.9218569 (xsd:string)
dcterms:issued 2020 (xsd:gYear)
rdfs:label Time-Division Multiplexing Based System-Level FPGA Routing for Logic Verification. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jianli_Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jun_Yu_0010>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Peng_Zou>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xiao_Shi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yao-Wen_Chang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yingjie_Wu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhifeng_Lin>
swrc:pages 1-6 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/dac/2020>
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owl:sameAs <http://dblp.rkbexplorer.com/id/conf/dac/ZouLSWCYC20>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/dac/dac2020.html#ZouLSWCYC20>
rdfs:seeAlso <https://doi.org/10.1109/DAC18072.2020.9218569>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/dac>
dc:title Time-Division Multiplexing Based System-Level FPGA Routing for Logic Verification. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document