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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/date/BeniniMMPS97>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Enrico_Macii>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Giovanni_De_Micheli>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Luca_Benini>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Massimo_Poncino>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Riccardo_Scarsi>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FEDTC.1997.582409>
foaf:homepage <https://doi.org/10.1109/EDTC.1997.582409>
dc:identifier DBLP conf/date/BeniniMMPS97 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FEDTC.1997.582409 (xsd:string)
dcterms:issued 1997 (xsd:gYear)
rdfs:label Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Enrico_Macii>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Giovanni_De_Micheli>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Luca_Benini>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Massimo_Poncino>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Riccardo_Scarsi>
swrc:pages 514-520 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/date/1997>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/date/BeniniMMPS97/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/date/BeniniMMPS97>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/date/edtc1997.html#BeniniMMPS97>
rdfs:seeAlso <https://doi.org/10.1109/EDTC.1997.582409>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/date>
dc:title Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document