Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/date/ChoLYCZ03
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Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design.
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Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design.
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